CIRCC datasheet(22/70 Pages) SMSC

22 / 70 page

REGISTERS

The CIrCC is partially enabled through binary

controls found in two 8-byte register banks. The

banks, the ACE550 UART Controls and the SCE

Controls, are selected with the nACE and nSCE

selector

inputs

found

the

Interface Description.

If nACE is zero, the three least significant bits of

the Host Address Bus decode the 16C550A

UART control registers.

If nSCE is zero, the

SCE control bank is addressed. All of the CIrCC

registers are 8 bits wide.

ACE UART CONTROLS

The table below (Table 12) lists the ACE UART

Control Registers.

See the current SMSC

16C550A

implementation

for

complete

description.

Table 12 - 16C550A UART Addressing

DLAB

DIRECTION

Read

Receive Buffer

Write

Transmit Buffer

Read/Write

Interrupt Enable

Read

Interrupt Identification

Write

FIFO Control

Read/Write

Line Control

Read/Write

Modem Control

Read/Write

Line Status

Read/Write

Modem Status

Read/Write

Scratchpad

Read/Write

Divisor (LSB)

Read/Write

Divisor (MSB)

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