CIRCC datasheet(32/70 Pages) SMSC

32 / 70 page

SCE Configuration Register B (Address 1)

Output Mux, bits 7 - 6

The

Output

Mux

bits

select

the

Output

Multiplexer port for the active encoder/decoder

(Table 20).

When D[7:6]=1,1 in Table 20

inactive outputs depend on the state of the Tx

Polarity bit, otherwise inactive outputs are zero.

The Output Mux bits are equivalent to the

FDC37C93x IR Option Register bits 6-7. The IR

Location Mux, bit 6, in the FDC37C93x IR Option

7 (Reserved) in the FDC37C93x IR Option

Provisions have been made in legacy devices to

accommodate Output Multiplexer port selection

through

either

the

chip-level

configuration

registers or the Output Mux bits; i.e., the last

write from either source determines the current

port selection and is visible in both registers.

Table 20 - CIrCC Output Multiplexer

MUX. MODE

Active Device to COM Port (default)

Active Device to IR Port

Active Device to AUX Port

Outputs Inactive

Loopback, bit 5

The Loopback bit configures the FIFO and

enables the transmitter/receiver for loopback

testing. The SCE MODES bits must be set to

zero before activating the Loopback bit. When

the Loopback bit is one, the SCE enters a full-

duplex mode with internal loopback capability for

testing. The 32-byte FIFO input is connected to

the SCE receiver output, the FIFO output is

connected to the SCE transmit input. Consumer

loopback

tests

reset

the

Loopback

bit

automatically when the Rx Data Size register

reaches

zero.

Provisions

must

made

following loopback tests in all modes to verify the

Rx message data in the FIFO.

CIRCC 데이터시트(PDF) 32 Page - SMSC Corporation

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