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M700000002 데이터시트(PDF) 80 Page - SPANSION |
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M700000002 데이터시트(HTML) 80 Page - SPANSION |
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80 / 128 page ![]() 78 Am70PDL127BDH/Am70PDL129BDH November 25, 2003 AD VAN C E INFORM ATION pSRAM ADDRESS SKEW Figure 30. Read Address Skew Note: If multiple invalid address cycles shorter than t RC min occur for a period greater than 10 µs, at least one valid address cycle over t RC min is required during that period. Figure 31. Write Address Skew Note: If multiple invalid address cycles shorter than t WC min occur for a period greater than 10 µs, at least one valid address cycle over t WC min, in addition to tWP min, is required during that period. CE#1ps WE# Address tRC min over 10 µs CE#1ps WE# Address tWP min tWC min over 10 µs |
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