2

(Continued)

This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to

be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1

second (if already completely preprogrammed). The MBM29F080A is erased when shipped from the factory.

The MBM29F080A device also features hardware sector group protection. This feature will disable both program

and erase operations in any combination of eight sector groups of memory.

A sector group consists of four

adjacent sectors grouped in the following pattern: sectors 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, and 14-15.

Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of

time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.

The device features single 5.0 V power supply operation for both read and program functions. Internally generated

inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of

been completed, the device automatically resets to the read mode.

The MBM29F080A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded

Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into

the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs

during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read

mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.

of quality, reliability, and cost effectiveness. The MBM29F080A memory electrically erases all bits within a sector

simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM

programming mechanism of hot electron injection.

s FEATURES

•

Single 5.0 V read, write, and erase

Minimizes system level power requirements

•

Compatible with JEDEC-standard commands

Pinout and software compatible with single-power supply Flash

Superior inadvertent write protection

•

48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)

40-pin TSOP(I) (Package Suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)

44-pin SOP (Package Suffix: PF)

•

Minimum 100,000 write/erase cycles

•

High performance

55 ns maximum access time

•

Sector erase architecture

Uniform sectors of 64 K bytes each

Any combination of sectors can be erased. Also supports full chip erase.

•

Embedded Erase™ Algorithms

Automatically pre-programs and erases the chip or any sector

•

Embedded Program™ Algorithms

Automatically programs and verifies data at specified address

•Data Polling and Toggle Bit feature for detection of program or erase cycle completion

•

Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

≤ 3.2 V

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