AD9937KCPRL datasheet(39/44 Pages) AD

39 / 44 page

REV. 0

AD9937

–39–

RS, H2(A, B), LM

ODD FIELD

EVEN FIELD

tDELAY3

tSETTINGS2

tPWR1

V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,

OFD, H1(A, B, C, D)

VDD

(INPUT)

(OUTPUT)

DIGITAL

OUTPUTS

VCKM

(OUTPUT)

SERIAL

WRITES

VCLK

OUTCONT

(REGISTER

CONTROLLED)

INTERNAL

POWER-ON

AUTO-RESET

(LO-ACTIVE)

NOTES

1THE INTERNAL POWER-ON AUTO RESET TIME t

PWR = 1.0ms REGARDLESS OF THE VCLK CLOCK FREQUENCY.

2IT TAKES 500 s FOR VCLK TO SETTLE ONCE THE DIG_STBY REGISTER HAS BEEN PROGRAMMED.

3IT TAKES FOUR VCKM CLOCK CYCLES FROM WHEN OUTCONT IS ASSERTED HIGH UNTIL THE VD, HD, AND DIGITAL OUTPUT DATA IS VALID.

Figure 37. Recommended Power-Up Sequence

POWER-UP FOR MASTER MODE

When the AD9937 is powered up, the following sequence is

recommended. (Refer to Figure 37 for each step.)

1. Turn on power supplies for AD9937.

2. The internal power-on auto-reset circuit will deassert

1.0 ms after VDD settles. (All internal registers are reset to

the default values.)

3. The VCKM clock can be applied as soon as VDD settles.

4. Reset the internal AD9937 registers: write a 0x000000 to

the SW_RESET register (addr 0x00). This will set all inter-

nal register values to their default values. (This step is optional

because the internal power-on reset circuit is applied at

power-up.)

5. Write a 1 to the DIG_STBY and AFE_STBY registers

(addr 0x02). This will put the digital and analog circuits into

the normal operating mode.

6. Program all control, system, and mode registers.

7. Write a 1 to the OUTCONT_REG (addr 0x01). This will put

the digital outputs into the normal operating mode. The inter-

nal OUTCONT will be asserted high on the rising edge of the

32nd SCK clock when writing to the OUTCONT_REG.

Table XVIII. Start-Up Polarities

(While OUTCONT = LO)

Output

OUTCONT = LO

V1A/B

V3A/B

TG1A

TG1B

TG3A

TG3B

OFD

H1(A–D)

H2(A, B)

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