AD9937KCPRL datasheet(21/44 Pages) AD

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REV. 0

AD9937

–21–

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9937 AFE signal processing chain is shown in Figure 11.

Each processing step is essential in achieving a high quality image

from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1

µF series coupling

capacitor. This restores the dc level of the CCD signal to approxi-

mately 1.5 V to be compatible with the 3 V analog supply of

the AD9937.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

diagram in Figure 13 illustrates how the two internally gener-

ated CDS clocks, SHP and SHD, are used to sample the

reference level and the data level, respectively, of the CCD

signal. The placement of the SHP and SHD sampling edges is

determined by the setting of the SHPLOC (addr 0x05) and

SHDLOC (addr 0x05) control registers. Placement of these two

clock edges is critical in achieving the best performance from

the CCD.

6dB TO 40dB

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

ADC

VGA

8-BIT

DAC

CLAMP LEVEL

VGA GAIN

CDS

INTERNAL

VREF

2V FULL

SCALE

PRECISION

TIMING

GENERATION

SHP

SHD

1.5V

OUTPUT

DATA

LATCH

REFT

REFB

DOUT

PHASE

V-H

TIMING

GENERATION

SHP

SHD

DOUT

PHASE

CLPOB

1.0V

2.0V

DOUT

1.0 F

CCDIN

AD9937

0.1 F

Figure 11. AFE Block Diagram

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