PCD5002 datasheet(19/48 Pages) PHILIPS

19 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

Fig.8 Message types.

handbook, full pagewidth

n bytes with acknowledge

FROM

MASTER

FROM

SLAVE

SLAVE ADDRESS

R/W

DATA

S = START condition

P = STOP condition

A = Acknowledge

N = Not acknowledge

n bytes with acknowledge

SLAVE ADDRESS

R/W

DATA

(a)

(b)

(c)

R/W

DATA

SL. ADR.

R/W

DATA

0 (write)

1 (read)

index

address

index

address

n bytes with

acknowledge

n bytes with

acknowledge

change of direction

INDEX

MLC250

(a) Master writes to slave.

(b) Master reads from slave.

8.25

Decoder I2C-bus access

All internal access to the PCD5002 takes place via the

I2C-bus interface. For this purpose the internal registers,

SRAM and EEPROM have been memory mapped and are

accessed via an index register. Table 16 shows the index

addresses of all internal blocks.

Registers are addressed directly, while RAM and

EEPROM are addressed indirectly via address pointers

and I/O registers.

Remark: The EEPROM memory map is non-contiguous

and is organized as a matrix.

The EEPROM address pointer contains both row and

column indicators.

Data written to read-only bits will be ignored. Values read

from write-only bits are undefined and must be ignored.

Each I2C-bus write message to the PCD5002 must start

with its slave address, followed by the index address of the

memory element to be accessed. An I2C-bus read

message uses the last written index address as a data

source. The different I2C-bus message types are shown in

Fig.8.

As a slave the PCD5002 cannot initiate bus transfers by

itself. To prevent an external controller from having to

monitor the operating status of the decoder, all important

events generate an external interrupt on output INT.

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