PCD5002 datasheet(23/48 Pages) PHILIPS

23 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

Table 21 Alert set-up register (04H; write)

Note

1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address codeword, which designate the

POCSAG call type as shown in Table 1.

BIT (MSB D7)

VALUE

DESCRIPTION

call alert via cadence register

POCSAG call alert (pattern selected by D7 and D6)

LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)

HIGH level acoustic alert (ATL + ATH), continuous vibrator alert

normal alerts (acoustic and LED)

warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate fAWH, fAWL)

acoustic alerts enable (ATL, ATH)

vibrator alert enabled (VIB)

LED alert enabled (LED)

D7 and D6(1)

0 0

POCSAG alert pattern FC = 00, see Fig.9 (a)

0 1

POCSAG alert pattern FC = 01, see Fig.9 (b)

1 0

POCSAG alert pattern FC = 10, see Fig.9 (c)

1 1

POCSAG alert pattern FC = 11, see Fig.9 (d)

Fig.9 POCSAG alert patterns.

handbook, full pagewidth

MLC251

(a)

(b)

(c)

(d)

0 0

D7, D6

0 1

1 0

1 1

PCD5002 데이터시트(PDF) 23 Page - NXP Semiconductors

PCD5002 데이터시트(HTML) 23 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

데이터시트 다운로드

링크 URL