PCD5003 datasheet(13/44 Pages) PHILIPS

13 / 44 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG Paging Decoder

PCD5003

Table 9

Call terminator bit identiﬁcation

Note

1. The DF bit in the call terminator is set:

a) When any call data codeword in the terminating batch was uncorrectable, while in ‘data receive’ mode.

b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a

user-programmed sync word, while in ‘data fail’ mode.

Table 10 Error type identiﬁcation (note 1)

Note

1. POCSAG code allows a maximum of 3 bit errors to be detected per codeword.

BITS (MSB to LSB)

IDENTIFICATION

forced call termination (1 = yes)

S3 to S1

identifier number of last sync word

data fail mode indication (1 = data fail mode); note 1

E3 to E1

detected error type; see Table 10; E3 = 0 in a call terminator

ERROR TYPE

NUMBER OF ERRORS

no errors - correct codeword

parity bit in error

single bit error

1 + parity

single bit error and parity error

not used

4-bit burst error and parity error

3 (e.g.1101)

2-bit random error

uncorrectable codeword

3 or more

Successful call termination occurs by reception of a valid

address codeword with less than 2 bit errors.

Unsuccessful termination occurs when sync word is not

detected while in ‘data fail’ mode.

It is generally possible to distinguish these two conditions

using the sync word identifier number (bits S3 to S1); the

identifier number will be non-zero for correct termination,

and zero for sync word failure.

Only when a call is received in ‘data fail’ mode and the call

is terminated before the end of the batch, is it not possible

to distinguish unsuccessful from correct termination.

Reception of message data can be terminated at any time

by transmitting a forced call termination command to the

control register via the I2C-bus. Any call received will then

be terminated immediately and ‘data fail’ mode will be

entered.

7.18

Receiver and oscillator control

A paging receiver and an RF oscillator circuit can be

controlled independently via enable outputs RXE and ROE

respectively. Their operating periods are optimized

according to the synchronization mode of the decoder.

Each enable signal has its own programmable

establishment time (see Table 11).

7.19

External receiver control and monitoring

An external controller may enable the receiver control

outputs continuously via an I2C-bus command, overruling

the normal enable pattern. Data reception continues

normally. This mode can be left by means of a reset or an

I2C-bus command.

External monitoring of the receiver control output RXE is

possible via bit D6 in the status register, when enabled via

the control register (D2 = 1). Each change of state of

output RXE will generate an external interrupt at

output INT.

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