1998 Apr 07

8

Philips Semiconductors

Objective specification

Universal LCD driver for small graphic

panels

PCF8558

ADDRESSING

The data is downloaded into the matrix of the PCF8558 as indicated in Figs 4 and 5.

The display RAM has a matrix of 40 by 101 bits (5 by 101 bytes). The columns are addressed by the address pointer.

After writing one byte the pointer is set to the next byte. Control of address increment, horizontal or vertical, is by bit V in

the command byte.

DATA STRUCTURE

Fig.4 RAM format, addressing.

handbook, full pagewidth

MGG561

display line 0 to 7

display line 8 to 15

display line 16 to 23

address 2

address 1

address 0

display line 24 to 31

display line 32 to 39

000

LSB

MSB

001

010

Y address

011

100

X

address 98

address 99

address 100

Fig.5 Order of writing data bytes into RAM.

16

27

38

49

MGG562

0

101

202

303

404

1

102

203

304

405

2

103

204

305

406

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