PCF8576CT datasheet(16/44 Pages) PHILIPS

16 / 44 page

1998 Jul 30

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex

rates

PCF8576C

6.11

Display RAM

The display RAM is a static 40

× 4-bit RAM which stores

LCD data. A logic 1 in the RAM bit-map indicates the on

state of the corresponding LCD segment; similarly, a

logic 0 indicates the off state. There is a one-to-one

correspondence between the RAM addresses and the

segment outputs, and between the individual bits of a RAM

word and the backplane outputs. The first RAM column

corresponds to the 40 segments operated with respect to

backplane BP0 (see Fig.10). In multiplexed LCD

applications the segment data of the second, third and

fourth column of the display RAM are time-multiplexed

with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8576C the

display bytes received are stored in the display RAM in

accordance with the selected LCD drive mode.

To illustrate the filling order, an example of a 7-segment

numeric display showing all drive modes is given in Fig.11;

the RAM filling organization depicted applies equally to

other LCD types.

With reference to Fig.11, in the static drive mode the eight

transmitted data bits are placed in bit 0 of eight successive

display RAM addresses.

In the 1 : 2 multiplex drive mode the eight transmitted data

bits are placed in bits 0 and 1 of four successive display

RAM addresses. In the 1 : 3 multiplex drive mode these

bits are placed in bits 0, 1 and 2 of three successive

addresses, with bit 2 of the third address left unchanged.

This last bit may, if necessary, be controlled by an

additional transfer to this address but care should be taken

to avoid overriding adjacent data because full bytes are

always transmitted. In the 1 : 4 multiplex drive mode the

eight transmitted data bits are placed in bits 0, 1, 2 and 3

of two successive display RAM addresses.

Table 3

LCD frame frequencies

PCF8576C MODE

FRAME

FREQUENCY

NOMINAL

FRAME

FREQUENCY

(Hz)

Normal mode

Power-saving mode

clk

2880

-------------

clk

480

----------

Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses

and segment outputs, and between bits in a RAM word and backplane outputs.

1234

display RAM addresses (rows) / segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

MBE525

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