PCF8579 datasheet(8/40 Pages) PHILIPS

8 / 40 page

1997 Apr 01

Philips Semiconductors

Product speciﬁcation

LCD column driver for dot matrix graphic

displays

PCF8579

FUNCTIONAL DESCRIPTION

The PCF8579 column driver is designed for use with the

PCF8578. Together they form a general purpose LCD dot

matrix chip set.

Typically up to 16 PCF8579s may be used with one

PCF8578. Each of the PCF8579s is identified by a unique

4-bit hardware subaddress, set by pins A0 to A3.

The PCF8578 can operate with up to 32 PCF8579s when

using two I2C-bus slave addresses. The two slave

addresses are set by the logic level on input SA0.

7.1

Multiplexed LCD bias generation

The bias levels required to produce maximum contrast

depend on the multiplex rate and the LCD threshold

voltage (Vth). Vth is typically defined as the RMS voltage at

which the LCD exhibits 10% contrast. Table 1 shows the

optimum voltage bias levels for the PCF8578/PCF8579

chip set as functions of Vop (Vop =VDD − VLCD), together

with the discrimination ratios (D) for the different multiplex

rates. A practical value for Vop is obtained by equating

Voff(rms) with Vth. Figure 4 shows the first 4 rows of Table 1

as graphs.

Table 1 Optimum LCD bias voltages

PARAMETER

MULTIPLEX RATE

1:8

1:16

1:24

1:32

0.739

0.800

0.830

0.850

0.522

0.600

0.661

0.700

0.478

0.400

0.339

0.300

0.261

0.200

0.170

0.150

0.297

0.245

0.214

0.193

0.430

0.316

0.263

0.230

1.447

1.291

1.230

1.196

3.370

4.080

4.680

5.190

---------

off rms

()

-----------------------

on rms

()

-----------------------

on rms

()

off rms

()

-----------------------

---------

7.2

Power-on reset

At power-on the PCF8579 resets to a defined starting

condition as follows:

1. Display blank (in conjunction with PCF8578)

2. 1 : 32 multiplex rate

3. Start bank, 0 selected

4. Data pointer is set to X, Y address 0, 0

5. Character mode

6. Subaddress counter is set to 0

7. I2C-bus is initialized.

Data transfers on the I2C-bus should be avoided for 1 ms

following power-on, to allow completion of the reset action.

Fig.4

Vbias/Vop as a function of the multiplex rate.

1:8

1:16

1:32

1.0

0.8

MSA838

1:24

0.6

0.4

0.2

multiplex rate

V bias

Vop

Vbias =V2, V3, V4, V5. See Table 1.

PCF8579 데이터시트(PDF) 8 Page - NXP Semiconductors

PCF8579 데이터시트(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

데이터시트 다운로드

링크 URL