PCF8579 datasheet(25/40 Pages) PHILIPS

25 / 40 page

1997 Apr 01

Philips Semiconductors

Product speciﬁcation

LCD column driver for dot matrix graphic

displays

PCF8579

13 AC CHARACTERISTICS

All timing values are referred to VIH and VIL levels with an input voltage swing of VSS to VDD.

VDD = 2.5 to 6 V; VSS =0V; VLCD =VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Note

1. Typically 0.9 to 3.3 kHz.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fclk

clock frequency

50% duty factor

−

note 1

kHz

tPLCD

driver delays

VDD − VLCD = 9 V; with test loads

−−

100

µs

I2C-bus

fSCL

SCL clock frequency

−−

100

kHz

tSW

tolerable spike width on bus

−−

100

tBUF

bus free time

4.7

−−µs

tSU;STA

START condition set-up time

repeated start codes only

4.7

−−µs

tHD;STA

START condition hold time

4.0

−−µs

tLOW

SCL LOW time

4.7

−−µs

tHIGH

SCL HIGH time

4.0

−−µs

SCL and SDA rise time

−−

1.0

µs

SCL and SDA fall time

−−

0.3

µs

tSU;DAT

data set-up time

250

−−

tHD;DAT

data hold time

−−

tSU;STO

STOP condition set-up time

4.0

−−µs

Fig.17 AC test loads.

MSA916

Ω

1.5 k

VDD

SDA

1 nF

C0 to C39

(2%)

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