PCF8593P datasheet(12/28 Pages) PHILIPS

12 / 28 page

1997 Mar 25

Philips Semiconductors

Product speciﬁcation

Low power clock/calendar

PCF8593

Fig.10 Alarm control register, event-counter mode.

handbook, full pagewidth

memory location 08

timer function :

000

no timer

001

units

010

100

011

10 000

100

1 000 000

101

not allowed

110

not allowed

111

test mode, all counters

in parallel

timer interrupt enable :

timer flag, no interrupt

timer flag, interrupt

clock alarm function :

no event alarm

event alarm

not allowed

11not allowed

timer alarm enable :

no timer alarm

timer alarm

alarm interrupt enable :

alarm flag, no interrupt

alarm flag, interrupt

654

321

MSB

LSB

MBD817

7.9

Interrupt output

The conditions for activating the open-drain n-channel

interrupt output INT (active LOW) are determined by

appropriate programming of the alarm control register.

These conditions are clock alarm, timer alarm, timer

overflow, and event counter alarm. An interrupt occurs

when the alarm flag or the timer flag is set, and the

corresponding interrupt is enabled. In all events, the

interrupt is cleared only by software resetting of the flag

which initiated the interrupt.

In the clock mode, if the alarm enable is not activated

(alarm enable bit of control/status register is logic 0), the

interrupt output toggles at 1 Hz with a 50% duty cycle (may

be used for calibration). The OFF voltage of the interrupt

output may exceed the supply voltage, up to a maximum

of 6.0 V. A logic diagram of the interrupt output is shown in

Fig.11.

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