AT83SND2CMP3 datasheet(23/97 Pages) ATMEL

23 / 97 page

AT83SND2CMP3

7524B–MP3–05/06

Figure 21. 20 bit I2S justified mode

Figure 22. 20 bit MSB justified mode

Figure 23. 20 bit LSB justified mode

The selection between modes is done using the DINTSEL 1:0 in DAC_MISC register

(Table 40.) according with the following table:

The data interface always works in slave mode. This means that the DSEL and the

DCLK signals are provided by microcontroller audio data interface.

Serial Audio DAC Interface

The serial audio DAC interface is a Synchronous Peripheral Interface (SPI) in slave

mode:

•

AUDCDIN: is used to transfer data in series from the master to the slave DAC.

It is driven by the master.

•

AUDCDOUT: is used to transfer data in series from the slave DAC to the master.

It is driven by the selected slave DAC.

•

Serial Clock (AUDCCLK): it is used to synchronize the data transmission both in

and out the devices through the AUDCDIN and AUDCDOUT lines.

Note:

Refer to Table 29. for DAC SPI Interface Description

L(N-1)

L(N-2)

L(N-3)

...

R(N-1)

R(N-2)

R(N-3)

...

SCLK

DSEL

DOUT

L(N-1)

L(N-2)

L(N-3)

...

R(N-1)

R(N-2)

R(N-3)

...

L(N-1)

SCLK

DSEL

DOUT

L(N-1)

L(N-2)

...

R(N-1)

R(N-2)

...

L(N-1)

SCLK

DSEL

DOUT

DINTSEL 1:0

Format

I2S Justified

MSB Justified

LSB Justified

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