ADMV8502ACCZ-R7 datasheet(11/32 Pages) AD

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Data Sheet

ADMV8502

THEORY OF OPERATION

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MODE SELECTION

The ADMV8502 has two modes of operation: SPI write and SPI

fast latch. SPI write mode is the normal operating mode, whereas

SPI fast latch mode is used to sequence through the on-chip

lookup table (LUT) using the internal state machine. To select SPI

write mode, set the SFL pin low. For operation in SPI fast latch

mode, program the on-chip LUT and fast latch parameters with the

SFL pin low, and then bring the SFL pin high to enter this mode.

Figure 21 shows a simplified representation of the SPI with the

flowchart in Figure 26 for the typical steps to operate in each mode.

Figure 21. Simplified SPI Diagram

SPI WRITE MODE

SPI write mode has a write grouping (WR) in Register 0x020

through Register 0x022. The grouping consists of the following:

►

fCENTER load value

►

Bandwidth load value

►

Match load value

See the Register Details section more information regarding the

write grouping.

SPI STREAMING

In general, there are two types of SPI streaming transactions, Endi-

an register ascending order and descending order. The ADMV8502

supports only the ascending order. To enable SPI streaming with

Endian register ascending order, program Register 0x000 to value

0x3C.

For SPI streaming to the write grouping, Register 0x020 to Register

0x022 (recommended), the transaction points to Register 0x020

and streams out 3 bytes of data. The transaction is 40 bits in total

(R/W bit + 15 bits address + 24 bits data).

For SPI streaming to the LUT, Register 0x100 to Register 0x15F

(recommended), the transaction points to Register 0x100 and

streams out 96 bytes of data. The transaction is 784 bits in total

(R/W bit + 15 bits address + 768 bits data).

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