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AS73211

Functional Description

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 19

Figure 17 shows the principle sequence for a measurement start in CMD mode coming from

Configuration state and waiting in Measurement state between the measurements is shown as IDLE:

OSR programming: 83h, change to Measurement state, start of measurement via

OSR:SS =

‚1‘,

“Automatically” OSR programming: 03h, to reset bit OSR:SS to ‚0‘ at the end of conversion.

Figure 17:

Principle Sequence for a Measurement Start in CMD Mode Coming From Configuration State

7.7

Synchronous Measurement Mode

– SYNS

In this measurement mode, the input pin SYN acts as a trigger event for the start of A/D conversion.

The falling edge at pin SYN starts the measurement. The conversion time (TCONV) is determined by

the content of the register CREG1:TIME (see Figure 48). The pin READY signalizes the progress of

conversion (see Figure 18) and its rising edge shows the end of conversion and its available valid

results. The data fetch should be performed between the rising edge of signal READY and the next

falling edge of signal SYN in order to allow distortion free measurement. SYN pulses during the

programmed pause time TBREAK are ignored to avoid a start of the measurement during a running

data fetch (see also Figure 52). The bit OSR:SS also takes effect in the SYNS mode, because the

start of the measurement is only possible with OSR:SS = ‚1‘.

Figure 18 shows the principle sequence for a measurement start in SYNS mode, OSR:DOS = 011b

and OSR:SS = ‚1‘ already set and waiting in Measurement state is shown as IDLE.

IDLE

MEASUREMENT 2

RESULTS 1

MEASUREMENT 1

CONFIGURATION

IDLE

TCONV

data

fetch

MRES1 …

MRES3

READY

STATE

I²C activity

RESULTS 2

TCONV

data

fetch

OSR:DOS = 011b

start (OSR:SS ← ,1')

clear (OSR:SS ← ,0')

start (OSR:SS ← ,1')

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