TMD2621 datasheet(30/59 Pages) OSRAM

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Datasheet, Public

Page 29

[v4-00] 2023-Apr-12

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TMD2621 − Register Overview

CFG3 Register (Address 0xAB)

Figure 42:

CFG3 Register

Addr: 0xAB

CFG3

Bit

Bit Name

Default

Access

Bit Description

7INT_READ_CLEAR

If set, the interrupt flag bits in the STATUS register

will be reset whenever the STATUS register is read

over I²C.

6:5

MODE_CFG

SAI is only available when MODE_CFG = 00b.

4SAI

The Sleep After Interrupt bit is used to place the

device into a low power mode at the end of the

proximity cycle if an interrupt has been generated.

SAI doesn't modify any register bits directly, it rather

uses the interrupt signal to turn off the oscillator.

The device will appear as if PON=0, however, PON

will read as 1. The way to wake up the device from

SAI-sleep is by clearing the interrupts in the status

registers. Note that SAI is only available when

MODE_CFG = 00b.

PON

SAI

INT (low

active)

Oscillator

OFF

3:0

Reserved

0001

Reserved. Must be set to default value.

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