TMG39921 datasheet(67/96 Pages) OSRAM

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[v1-06] 2018-Feb-27

TMG3992 − Register Description

Configuration Register A5 (CONFIG_A5),

IRBeam Mode

While IRBeam is enabled, this register defines the length of time

that the LDR pin is disabled (i.e. LED is turned OFF) between

consecutive Packet loops. The following equation governs the

time delay:

The minimum typical inter-Packet LED OFF time is 1.0 μs. The

maximum typical inter-Packet LED OFF time 17.7ms.

Figure 69:

Configuration Register A5

Configuration Register A6 (CONFIG_A6),

IRBeam Mode

While in IRBeam mode, this register selects the pulse width of

one bit-time. This is fundamental time period for pattern

generation.

The minimum typical bit-time 0.27μs (IBT = 0). The maximum

typical bit-time is 17.28μs (IBT = 0x3F).

Figure 70:

Configuration Register A6

The IRBeam bit time is set by the following equation:

765

432

IPOFF

Field

Bits

Description

IPOFF

7:0

IRBeam Packet OFF Delay Time. Sets the amount of LED OFF time

between Packets.

765

432

Reserved

IBT

Field

Bits

Description

Reserved

7:6

Reserved. Bits must be set to 0 in IRBeam mode.

IBT

5:0

IRBeam Bit Time. Defines the pulse width for one bit-time.

(EQ8)

tIPDT

IPOFF 1

()

tIBT

(EQ9)

tIBT

IBT 1

() 0.27μs

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