TSL2580FN datasheet(24/53 Pages) OSRAM

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ams Datasheet

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[v1-00] 2016-Apr-05

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TSL2580, TSL2581 − Register Set

Interrupt Register (02h)

The INTERRUPT register controls the extensive interrupt

capabilities of the device. The open-drain interrupt pin is active

low and requires a pull-up resistor to VDD in order to pull high

in the inactive state. The TSL258x permits both SMB-Alert style

interrupts as well as traditional level style interrupts. The

Interrupt Register provides control over when a meaningful

interrupt will occur. The concept of a meaningful change can

be defined by the user both in terms of light intensity and time,

or persistence of that change in intensity. The value must cross

the threshold (as configured in the Threshold Registers 03h

through 06h) and persist for some period of time as outlined in

Figure 30.

When a level Interrupt is selected, an interrupt is generated

whenever the last conversion results in a value outside of the

programmed threshold window. The interrupt is active-low and

remains asserted until cleared by writing an 11 in the

TRANSACTION field in the COMMAND register.

In SMB-Alert mode, the interrupt is similar to the traditional

level style and the interrupt line is asserted low. To clear the

interrupt, the host responds to the SMB-Alert by performing a

modified Receive Byte operation, in which the Alert Response

Address (ARA) is placed in the slave address field, and the

TSL258x that generated the interrupt responds by returning its

own address in the seven most significant bits of the receive

data byte. If more than one device connected on the bus has

pulled the SMBAlert line low, the highest priority (lowest

address) device will win control of the bus during the slave

address transfer. If the device loses this arbitration, the

interrupt will not be cleared. The Alert Response Address is 0Ch.

When INTR = 11, the interrupt is generated immediately

following the SMBus write operation. Operation then behaves

in an SMB-Alert mode, and the software set interrupt may be

cleared by an SMB-Alert cycle.

Note(s): Interrupts are based on the value of Channel 0 only.

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