56F8322 datasheet(90/136 Pages) FREESCALE

90 / 136 page

56F8322 Techncial Data, Rev. 16

Freescale Semiconductor

Preliminary

6.5.9.1

Reserved—Bits 15–14

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.2

Analog-to-Digital Converter A Enable (ADCA)—Bit 13

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.3

FlexCAN Enable (CAN)—Bit 12

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.4

Reserved—Bit 11

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.5

Decoder 0 Enable (DEC0)—Bit 10

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.6

Reserved—Bit 9

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.7

Quad Timer C Enable (TMRC)—Bit 8

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.8

Reserved—Bit 7

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.9

Quad Timer A Enable (TMRA)—Bit 6

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

56F8322 데이터시트(PDF) 90 Page - Freescale Semiconductor, Inc

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