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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 42

Start AD

ADC Stabilization

Output Mode

ADC Time [clocks]

ADC Response

Stabilization ON

Status6Reg[0] = ' 1 '

8-Bit Mode

Status2Reg[3] = ' 1 '

34 + ROUNDUP(EOR_value + 1) = 290

12-Bit Mode

Status2Reg[3] = ' 0 '

34 + ROUNDUP((EOR_value + 1) / 1.5) = 717

(Default)

Auto Start AD ON

Status2Reg[4] = ' 1 '

ADC Response

Stabilization OFF

Status6Reg[0] = ' 0 '

8-Bit Mode

Status2Reg[3] = ' 1 '

20 + ROUNDUP(EOR_value + 1) = 276

12-Bit Mode

Status2Reg[3] = ' 0 '

20 + ROUNDUP((EOR_value + 1) / 1.5) = 703

ADC Response

Stabilization ON

Status6Reg[0] = ' 1 '

8-Bit Mode

Status2Reg[3] = ' 1 '

30 + ROUNDUP(EOR_value + 1) = 286

12-Bit Mode

Status2Reg[3] = ' 0 '

30 + ROUNDUP((EOR_value + 1) / 1.5) = 713

(1)

Validation tests were performed using these ADC times, for the respective output modes.

Figure 62 shows in detail the ADC Ramp and all the conversion process. Pending on the ADC

configuration, the ADC Time will be different, which may influence the pixel timing minimum number of

clocks:

Figure 62:

Sensor Timing According To The ADC Configuration(1)

(1)

The times identified by numbers are in line with Figure 58.

Assuming that the ADC Time is much higher than the Readout Time, the sensor Full Cycle Timing

(FCT) needs to take in consideration all the diagrams times, to not incur on timing violations.

(A)

(B)

(D)

Exposure Time

Conversion Time

TBTW_SAMPLE&START_AD = (I)

Exposure Time

Conversion Time

TBTW_RESETS

20 clocks

30 clocks

24 clocks

34 clocks

ROUNDUP(EOR_VALUE + 1)

ROUNDUP(EOR_VALUE + 1)/1.5

ADC Time

RST_CVC

RST_CDS

SAMPLE

Start_AD

RST_RAMP

RST_COUNTER

RAMP

Conversion Time

TBTW_START_AD&RST_RAMP = 1 clock

(E)

Full Cycle Timing (FCT)

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