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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 65

Information

The information in the section above needs to be aligned with the sensor configuration as

provided in the common upload file. Make sure to check the latest version of datasheet

and common upload files on the ams.com product page under Tools & Resources.

In addition to the Common Upload sequence, an additional SPI write is required to indicate if

the sensor has a monochrome pixel array, or includes the Bayer RGB color pattern. Configure

the sensor according to Figure 70. Besides the COLOR_MODE, also 2 additional registers

need to be set when using a color sensor in binning mode according to Figure 71. Make sure

not to overwrite other bits of register 118.

Figure 70:

Color Mode

Bank

Address

Bits

Description

COLOR_MODE

[0]

0: Mono

1: Color

Figure 71:

Only set in case of 12b binning mode

Bank

Address

Bits

Description

118

[10:7]

5: Mono (default)

3: Color

118

[19:16]

5: Mono (default)

3: Color

Set PLL

Starting from the input clock frequency and the targeted output data rate, 4 parameters must

be calculated to correctly configure the PLL. Then the PLL must be configured using the

upload sequence below.

Figure 72:

PLL Configuration Sequence

Bank

Address

Value

PLL_DIV

See calculation below

PLL_WRAP_ADC_DIV

See calculation below

PLL_WRAP_MAIN_DIV

See calculation below

PLL_RST_N

Wait at least 10 µs

PLL_PD_N

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