MPC8323CVRADDC datasheet(11/80 Pages) FREESCALE

11 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Clock Input Timing

NOTE

AVDDn (1.0 V) is estimated to consume 0.05 W (under normal operating

conditions and ambient temperature).

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8323E.

4.1

DC Electrical Characteristics

Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8323E.

4.2

AC Electrical Characteristics

The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending

on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the MPC8323E.

Table 7. CLKIN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.7

OVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

CLKIN input current

0 V

≤ VIN ≤ OVDD

IIN

—±5

μA

PCI_SYNC_IN input current

0 V

≤ VIN ≤ 0.5 V or

OVDD – 0.5 V ≤ VIN ≤ OVDD

IIN

—±5

μA

PCI_SYNC_IN input current

0.5 V

≤ VIN ≤ OVDD – 0.5 V

IIN

—±50

μA

Table 8. CLKIN AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

CLKIN/PCI_CLK frequency

fCLKIN

—

66.67

MHz

CLKIN/PCI_CLK cycle time

tCLKIN

—

CLKIN/PCI_CLK rise and fall time

tKH, tKL

0.6

0.8

1.2

CLKIN/PCI_CLK duty cycle

tKHK/tCLKIN

—

CLKIN/PCI_CLK jitter

—

±150

4, 5

Notes:

1. Caution: The system, core, security, and QUICC Engine block must not exceed their respective maximum or minimum

operating frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

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