AD9910SLASHPCBZ datasheet(28/60 Pages) AD

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AD9910

Rev. 0 | Page 28 of 60

The direction of the ramping function is controlled by the

DRCTL pin. A Logic 0 on this pin causes the DRG to ramp

with a negative slope, whereas a Logic 1 causes the DRG to

ramp with a positive slope.

The DRG also supports a hold feature controlled via the DRHOLD

pin. When this pin is Logic 1, the DRG is stalled at its last state,

otherwise, the DRG operates normally.

The DDS signal control parameters that are not the destination of

the DRG are taken from the active profile.

DDS CLOCK

LOWER

LIMIT

DECREMENT STEP SIZE

PRESET

DRCTL

LOAD

CLEAR DIGITAL RAMP ACCUMULATOR

AUTOCLEAR DIGITAL RAMP ACC

NO DWELL

LIMIT CONTROL

DIGITALRAMP ACCUMULATOR

INCREMENT STEP SIZE

NEGATIVE SLOPE RATE

POSITIVE SLOPE RATE

DRHOLD 63

LOAD

CONTROL

LOGIC

LOAD LRR AT I/O_UPDATE

DIGITAL

RAMP

TIMER

ACCUMULATOR

RESET

CONTROL

LOGIC

NO-DWELL

CONTROL

TO DDS

SIGNAL

CONTROL

PARAMETER

UPPER

LIMIT

Figure 38. Digital Ramp Generator Detail

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