TMS320VC5402 datasheet(20/68 Pages) TI

20 / 68 page

TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multichannel buffered serial ports

The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow

direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based

on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:

D Full-duplex communication

D Double-buffered data registers, which allow a continuous data stream

D Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

D Direct interface to:

–

T1/E1 framers

–

MVIP switching compatible and ST-BUS compliant devices

–

IOM-2 compliant devices

–

Serial peripheral interface devices

D Multichannel transmit and receive of up to 128 channels

D A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

D µ-law and A-law companding

D Programmable polarity for both frame synchronization and data clocks

D Programmable internal clock and frame generation

The McBSPs consist of separate transmit and receive channels that operate independently. The external

interface of each McBSP consists of the following pins:

D BCLKX

Transmit reference clock

D BDX

Transmit data

D BFSX

Transmit frame synchronization

D BCLKR

Receive reference clock

D BDR

Receive data

D BFSR

Receive frame synchronization

The six pins listed are functionally equivalent to previous serial port interface pins in the ’C5000 family of DSPs.

On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins,

respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR).

Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows

DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

TMS320VC5402 데이터시트(PDF) 20 Page - Texas Instruments

TMS320VC5402 데이터시트(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

데이터시트 다운로드

링크 URL