DSP56374UMSLASHD datasheet(13/64 Pages) FREESCALE

13 / 64 page

Signal Groupings

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

FSR

Input or output

GPIO

disconnected

Frame Sync for Receiver—This is the receiver frame sync

input/output signal. In the asynchronous mode (SYN=0),

the FSR pin operates as the frame sync input or output

used by all the enabled receivers. In the synchronous mode

(SYN=1), it operates as either the serial flag 1 pin

(TEBE=0), or as the transmitter external buffer enable

control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is

determined by the RFSD bit in the RCCR register. When

configured as the output flag OF1, this pin will reflect the

value of the OF1 bit in the SAICR register, and the data in

the OF1 bit will show up at the pin synchronized to the

frame sync in normal mode or the slot in network mode.

When configured as the input flag IF1, the data value at the

pin will be stored in the IF1 bit in the SAISR register,

synchronized by the frame sync in normal mode or the slot

in network mode.

PC1

Input, output, or

disconnected

Port C1—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant.

FST

Input or output

GPIO

disconnected

Frame Sync for Transmitter—This is the transmitter frame

sync input/output signal. For synchronous mode, this signal

is the frame sync for both transmitters and receivers. For

asynchronous mode, FST is the frame sync for the

transmitters only. The direction is determined by the

transmitter frame sync direction (TFSD) bit in the ESAI

transmit clock control register (TCCR).

PC4

Input, output, or

disconnected

Port C4—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant.

Table 10. Enhanced Serial Audio Interface Signals (continued)

Signal Name

Signal Type

State during

Reset

Signal Description

DSP56374UM/D 데이터시트(PDF) 13 Page - Freescale Semiconductor, Inc

DSP56374UM/D 데이터시트(HTML) 13 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

데이터시트 다운로드

링크 URL