PAC7112 datasheet(20/56 Pages) FREESCALE

20 / 56 page

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Electrical Characteristics

Freescale Semiconductor

3.9

External Bus Timing

Table 24 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and output delay

with respect to the rising edge of a reference clock. The reference clock is the

CLKOUT output. All other timing relationships can be derived from these values.

Figure 6. General Input Timing Requirements

Table 24. External Bus Input Timing Specifications 1

NOTES:

1. Assumes CLKOUT is configured for full drive strength (via the PIM CONFIG2_D[RDS] bit).

Num

Rating

Symbol

Min

Max

Unit

P CLKOUT period 2

2. CLKOUT is equal to the system clock, fSYS. If CLKSEL[PLLSEL] is set then fSYS is equal to fVCO (table Table 20,

K3); if it is clear then fSYS is equal to fOSC (table Table 19, J1a or J1b). Throughout this document, tCYC is used to

specify a unit of time equal to 1

÷ CLKOUT (which is equal to t

fsys).

tCYC

—

Control Inputs

M2a

P Control input valid to CLKOUT high 3

3. The TA pin is the only control input on MAC7100 family devices.

tCVCH

—

M3a

P CLKOUT high to control inputs invalid 3

tCHCII

0—

Data Inputs

P Data input (DATA[15:0]) valid to CLKOUT high

tDIVCH

9—

P CLKOUT high to data input (DATA[15:0]) invalid

tCHDII

0—

CLKOUT (50 MHz)

1.5 V

Valid

Invalid

tSETUP

tHOLD

Input Setup & Hold

Input Rise Time

VH = VIH

VL = VIL

tRISE = 1.5 ns

Input Fall Time

VH = VIH

VL = VIL

tFALL = 1.5 ns

CLKOUT

Inputs

1.5 V

PAC7112 데이터시트(PDF) 20 Page - Freescale Semiconductor, Inc

PAC7112 데이터시트(HTML) 20 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

데이터시트 다운로드

링크 URL