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56F8167 데이터시트(PDF) 65 Page - Freescale Semiconductor, Inc |
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56F8167 데이터시트(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 184 page ![]() Peripheral Memory Mapped Registers 56F8367 Technical Data, Rev. 8 Freescale Semiconductor 65 Preliminary Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Register SCI0_SCIDR $4 Data Register Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym Address Offset Register Description SCI1_SCIBR $0 Baud Rate Register SCI1_SCICR $1 Control Register Reserved SCI1_SCISR $3 Status Register SCI1_SCIDR $4 Data Register Table 4-25 Serial Peripheral Interface 0 Registers Address Map (SPI0_BASE = $00 F2A0) Register Acronym Address Offset Register Description SPI0_SPSCR $0 Status and Control Register SPI0_SPDSR $1 Data Size Register SPI0_SPDRR $2 Data Receive Register SPI0_SPDTR $3 Data Transmitter Register Table 4-26 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00 F2B0) Register Acronym Address Offset Register Description SPI1_SPSCR $0 Status and Control Register SPI1_SPDSR $1 Data Size Register SPI1_SPDRR $2 Data Receive Register SPI1_SPDTR $3 Data Transmitter Register |
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