56F8167 datasheet(91/184 Pages) FREESCALE

91 / 184 page

56F8367 Technical Data, Rev. 8

Freescale Semiconductor

Preliminary

5.6.4.7

FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.4.8

Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.5

Interrupt Priority Register 4 (IPR4)

Figure 5-7 Interrupt Priority Register 4 (IPR4)

5.6.5.1

SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)—Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.5.2

SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)—

Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

Base + $4

Read

SPI0_RCV

IPL

SPI1_XMIT

IPL

SPI1_RCV

IPL

GPIOA IPL

GPIOB IPL

GPIOC IPL

Write

RESET

0000000

000

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