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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC855T 데이터시트(PDF) 12 Page - Freescale Semiconductor, Inc |
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MPC855T 데이터시트(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 80 page  MPC860 Family Hardware Specifications, Rev. 7 12 Freescale Semiconductor Bus Signal Timing All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of 6 inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. 9 Bus Signal Timing Table 7 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz. The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus). The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. Table 7. Bus Operation Timings Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max B1 CLKOUT period 30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns B1a EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz and MF <= 2) –0.90 0.90 –0.90 0.90 –0.90 0.90 –0.90 0.90 ns B1b EXTCLK to CLKOUT phase skew (EXTCLK > 10 MHz and MF < 10) –2.30 2.30 –2.30 2.30 –2.30 2.30 –2.30 2.30 ns B1c CLKOUT phase jitter (EXTCLK > 15 MHz and MF <= 2) 1 –0.60 0.60 –0.60 0.60 –0.60 0.60 –0.60 0.60 ns B1d CLKOUT phase jitter1 –2.00 2.00 –2.00 2.00 –2.00 2.00 –2.00 2.00 ns B1e CLKOUT frequency jitter (MF < 10) 1 — 0.50 — 0.50 — 0.50 — 0.50 % B1f CLKOUT frequency jitter (10 < MF < 500) 1 — 2.00 — 2.00 — 2.00 — 2.00 % B1g CLKOUT frequency jitter (MF > 500) 1 — 3.00 — 3.00 — 3.00 — 3.00 % B1h Frequency jitter on EXTCLK 2 — 0.50 — 0.50 — 0.50 — 0.50 % B2 CLKOUT pulse width low 12.12 — 10.00 — 8.00 — 6.06 — ns B3 CLKOUT width high 12.12 — 10.00 — 8.00 — 6.06 — ns B4 CLKOUT rise time 3 — 4.00 — 4.00 — 4.00 — 4.00 ns B533 CLKOUT fall time3 — 4.00 — 4.00 — 4.00 — 4.00 ns B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) invalid 7.58 — 6.25 — 5.00 — 3.80 — ns |
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