OXCF950 datasheet(52/66 Pages) OXFORD

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DS-0027 Feb 06

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OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

6.11.12 Good-data status register ‘GDS’

The GDS register is located at offset 0x10 of the ICR

Good data status is set when the following conditions are

true:

•

ISR reads level0 (no interrupt), level2 or 2a

(receiver data) or level3 (THR empty) interrupt.

•

LSR[7] is clear i.e. no parity error, framing error

or break in the FIFO.

•

LSR[1] is clear i.e. no overrun error has occurred.

GDS[0]: Good Data Status

GDS[7:1]: Reserved

6.11.13 DMA Status Register ‘DMS’

The DMS register is located at offset 0x11 of the ICR. This

purposes.

6.11.14 Port Index Register ‘PIX’

The PIX register is located at offset 0x12 of the ICR. This

read-only register gives the UART index. For a single

channel device such as the OXCF950 this reads ‘0’.

6.11.15 Clock Alteration Register ‘CKA’

The CKA register is located at offset 0x13 of the ICR. This

isochronous and embedded applications. The register is

effectively an enhancement to the CKS register.

This register is cleared to 0x00 after a hardware reset to

maintain compatibility with 16C550, but is unaffected by

software reset. This allows the user to select a clock mode

and then reset the channel to work-around any timing

glitches.

CKA[0]: Invert internal RX Clock

This allows the sense of the receiver clock to be inverted.

The main use for this would be to invert an isochronous

input clock so the falling edge were used for sampling

rather than the rising edge.

CKA[1]: Invert internal TX clock

This allows the sense of the transmitter clock to be

inverted. The main use for this would be to invert an

isochronous input clock so the rising edge were used for

data output rather than the falling edge.

CKA[2]: Invert DTR

This allows the DTR output signal to be inverted, which is

most likely to be useful when DTR is selected as being the

transmitter clock for isochronous applications.

6.11.16 Misc Data Register

The Misc Data Register allows the user to select access to

either the local configuration registers or the local bus,

when the OXCF950 is operating in Local Bus Mode. When

the OXCF950 is operating in Generic mode (8 byte

address space), it causes the local configuration registers

to overlay the UART registers. It has no effect when the

OXCF950 is operating in Normal Mode. When exiting

generic mode access to configuration registers, b0 is

cleared automatically.

Table 40 describes the MDR register operation.

MDR

Bits

Description

7:1

Reserved for future use : ‘0’ must be written to

these.

Active low Local Bus Enable (Local Bus

mode only).

Setting this bit to ‘0’ allows access to local bus.

Setting this bit to ‘1’ allows access to local

configuration registers.

Table 40: MDR operation

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