MPC8540CPX667JC datasheet(2/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

1 Overview

The following section provides a high-level overview of the MPC8540 features. Figure 1 shows the major

functional units within the MPC8540.

Figure 1. MPC8540 Block Diagram

1.1 Key Features

The following lists an overview of the MPC8540 feature set.

•

High-performance, 32-bit Book E–enhanced core that implements the Power Architecture

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can

be locked entirely or on a per-line basis. Separate locking for instructions and data

— Memory management unit (MMU) especially designed for embedded applications

— Enhanced hardware and software debug support

— Performance monitor facility (similar to but different from the MPC8540 performance monitor

described in Chapter 18, “Performance Monitor.”

I2C

Local Bus Controller

Programmable

RapidIO Controller

PCI/PCI-X Controller

4ch DMA Controller

DDR SDRAM Controller

256KB

L2-Cache/

SRAM

e500 Core

32 KB L1

I Cache

32 KB L1

D Cache

Core Complex Bus

e500

Coherency

Module

OCeaN

16 Gb/s

RapidIO-8

133 MHz

PCI-X 64b

TSEC

10/100/1G

MII, GMII,TBI,

RTBI, RGMII

MII, GMII,TBI,

RTBI, RGMII

10/100

ENET

MII

DUART

Serial

IRQs

SDRAM

DDR

ROM,

TSEC

10/100/1G

Interrupt Controller

SDRAM,

GPIO

I2C

Controller

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