MPC8540CVT667JC datasheet(60/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

RapidIO

The compliance of driver output signals TD[0:15] and TFRAME with their minimum data valid window

(DV) specification shall be determined by generating an eye pattern for each of the data signals and

comparing the eye pattern of each data signal with the RapidIO transmit mask shown in Figure 37. The

value of X2 used to construct the mask shall be (1 – DVmin)/2. A signal is compliant with the data valid

window specification if the transmit mask can be positioned on the signal’s eye pattern such that the eye

pattern falls entirely within the unshaded portion of the mask.

Figure 37. RapidIO Transmit Mask

Table 49. RapidIO Driver AC Timing Specifications—1 Gbps Data Rate

Characteristic

Symbol

Range

Unit

Notes

Min

Max

Differential output high voltage

VOHD

200

540

Differential output low voltage

VOLD

–540

–200

Duty cycle

2, 6

VOD rise time, 20%–80% of peak to peak

differential signal swing

tFALL

100

—

3, 6

VOD fall time, 20%–80% of peak to peak

differential signal swing

tRISE

100

—

Data valid

575

—

Skew of any two data outputs

tDPAIR

—

100

4, 6

Skew of single data outputs to associated clock

tSKEW,PAIR

–100

100

5, 6

Notes:

1.See Figure 37.

2.Requires ±100 ppm long term frequency stability.

3.Measured at VOD = 0 V.

4.Measured using the RapidIO transmit mask shown in Figure 37.

5.See Figure 42.

6.Guaranteed by design.

VOHDmax

VOHDmin

VOLDmax

VOLDmin

1–X2

Time (UI)

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