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© Andigilog, Inc. 2006
www.andigilog.com
October 2006 - 70A06010
aSC7621
Bit
Name
R/W
Default
Description
0
2.5V Limits
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the 2.5V input voltage is
less than or equal to the limit set in the 2.5V Low Limit register or greater than
the limit set in the 2.5V High Limit register.
1
Vccp Limits
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the VCCP input voltage is
less than or equal to the limit set in the VCCP Low Limit register or greater
than the limit set in the VCCP High Limit register.
2
3.3V Limits
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the 3.3V input voltage is
less than or equal to the limit set in the 3.3V Low Limit register or greater than
the limit set in the 3.3V High Limit register.
3
5V Limits
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the 5V input voltage is less
than or equal to the limit set in the 5V Low Limit register or greater than the
limit set in the 5V High Limit register.
4
Zone 1 Limit
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the temperature input
measured by the Remote1- and Remote1+ inputs is less than or equal to the
limit set in the Processor (Zone 1) Low Temp register or more than the limit set
in the Processor (Zone 1) High Temp register. This bit will be set when a
diode fault is detected.
5
Zone 2 Limit
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the temperature input
measured by the internal temperature sensor is less than or equal to the limit
set in the thermal (Zone 2) Low Temp register or greater than the limit set in
the Internal (Zone 2) High Temp register.
6
Zone 3 Limit
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the temperature input
measured by the second remote temperature sensor is less than or equal to
the limit set in the thermal (Zone 3) Low Temp register or greater than the limit
set in the Internal (Zone 3) High Temp register.
7
Error in Status
Register 2
R
0
If there is a set bit in Status Register 2, this bit will be set to 1.
Table 12 Interrupt Status Register 1
Register 42h: Interrupt Status Register 2
Register
Address
Read/
Write
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
42h
R
Interrupt Status 2
ERR2
ERR1
FAN4
FAN3
FAN2
FAN1
ERR
12V
N/A
The Interrupt Status Register 2 bits will be automatically set, by the aSC7621, whenever a fault condition is detected.
Interrupt Status Register 2 identifies faults caused by temperature sensor error, fan speed dropping below minimum set by
the tachometer minimum register. Interrupt Status Register 2 will hold a set bit until the event is read by software. The
contents of this register will be cleared (set to 0) automatically by the aSC7621 after it is read by software, if fault condition
no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read event occurs, even if the fault no
longer exists. This register is read-only – a write to this register has no effect.
Bit
Name
R/W
Default
Description
0
12V Limits
Exceeded
R
0
The aSC7621 automatically sets this bit to 1 when the 12V input voltage is
less than or equal to the limit set in the 12V Low Limit register or greater than
the limit set in the 12V High Limit register.
1
ERROR IN
STATUS
REGISTER 3
R
0
If there is a set bit in Status Register 3, this bit will be set to 1
2
FAN 1
STALLED
R
0
The aSC7621 automatically sets this bit to 1 when the TACH 1 input reading is
above the count value set in the Tach 1 Minimum MSB and LSB registers.
3
FAN 2
STALLED
R
0
The aSC7621 automatically sets this bit to 1 when the TACH 2 input reading is
above the count value set in the Tach 2 Minimum MSB and LSB registers.
4
FAN 3
STALLED
R
0
The aSC7621 automatically sets this bit to 1 when the TACH 3 input reading is
above the count value set in the Tach 3 Minimum MSB and LSB registers.
5
FAN 4
STALLED
R
0
The aSC7621 automatically sets this bit to 1 when the TACH 4 input reading is
above the count value set in the Tach 4 Minimum MSB and LSB registers.