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© Andigilog, Inc. 2006
www.andigilog.com
October 2006 - 70A06010
aSC7621
Serial Port Timing
(TA = 25 °C, VDD = 3.3V unless otherwise noted, Guaranteed by design, not production tested)
Parameter
Symbol
Min
Typ
Max
Units
SCL Operating Frequency
fSCL
400
kHz
SCL Clock Transition Time
tT:LH , tT:HL
300
ns
SCL Clock Low Period
tLOW
1.3
μs
SCL Clock High Period
tHIGH
0.6
50
μs
Bus free time between a Stop and a new Start Condition
tBUF
1.3
μs
Data in Set-Up to SCL High
tSU:DAT
100
ns
Data Out Stable after SCL Low
tHD:DAT
300
ns
SCL Low Set-up to SDA Low (Repeated Start Condition)
tSU:STA
600
ns
SCL High Hold after SDA Low (Start Condition)
tHD:STA
600
ns
SDA High after SCL High (Stop Condition)
tSU:STO
600
ns
Time in which aSC7621 must be operational after a power-on reset
tPOR
500
ms
SMBus Time-out before device communication interface reset
10
tTIMEOUT
25
35
ms
Notes (cont’d):
5. These specifications are guaranteed only for the test conditions listed.
6. The accuracy of the aSC7621 is guaranteed when using the thermal diode of Intel Pentium 4, 65nm processors or any thermal
diode with a non-ideality of 1.009 and series resistance of 4.52Ω. When using a 2N3904 type transistor or an CPU with a
different non-ideality the error band will be typically shifted depending on transistor diode or CPU characteristics. See
applications section for details.
7. Accuracy (expressed in °C) = Difference between the aSC7621 reported output temperature and the temperature being
measured. Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating
is the product of the internal power dissipation of the aSC7621 and the thermal resistance. See (Note 3) for the thermal
resistance to be used in the self-heating calculation.
8. TUE, total unadjusted error, includes ADC gain, offset, linearity and reference errors. TUE is defined as the “actual
Vin” to
achieve a given code transition minus the “theoretical
Vin “ for the same code. Therefore, a positive error indicates that the input
voltage is greater than the theoretical input voltage for a given code. If the theoretical input voltage was applied to an aSC7621
that has positive error, the aSC7621’s reading would be less than the theoretical.
9. This specification is provided only to indicate how often temperature and voltage data is updated. The aSC7621 can be read at
any time without regard to conversion state (and will yield last conversion result).
10. Holding the SMBCLK line low for a time interval greater than tTIMEOUT will reset the aSC7621’s SMBus state machine, therefore
setting the SMBDAT pin to a high impedance state.
tHD:STA
tSU:STO
tSU:DAT
SCL
SDA
tBUF
tSU:STA
tHD:DAT
SCL
SDA
Data Out
10
10
90
tT:LH
tT:HL
tLOW
tHIGH
90
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