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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MB95F133JS 데이터시트(PDF) 46 Page - fujitsu semiconductor |
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MB95F133JS 데이터시트(HTML) 46 Page - fujitsu semiconductor |
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46 / 63 page  MB95130M Series 46 Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Sym- bol Pin name Condition Value Unit Min Max Serial clock cycle time tSCYC SCK Internal clock operation output pin : CL = 80 pF + 1 TTL. 5 tMCLK*3 ⎯ ns SCK ↑→ SOT delay time tSHOVI SCK, SOT − 95 +95 ns Valid SIN → SCK↓ tIVSLI SCK, SIN tMCLK*3 + 190 ⎯ ns SCK ↓→ valid SIN hold time tSLIXI SCK, SIN 0 ⎯ ns Serial clock “H” pulse width tSHSL SCK External clock operation output pin : CL = 80 pF + 1 TTL. 3 tMCLK*3 − tR ⎯ ns Serial clock “L” pulse width tSLSH SCK tMCLK*3 + 95 ⎯ ns SCK ↑ → SOT delay time tSHOVE SCK, SOT ⎯ 2 tMCLK*3 + 95 ns Valid SIN → SCK↓ tIVSLE SCK, SIN 190 ⎯ ns SCK ↓→ valid SIN hold time tSLIXE SCK, SIN tMCLK*3 + 95 ⎯ ns SCK fall time tF SCK ⎯ 10 ns SCK rise time tR SCK ⎯ 10 ns |
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