MB95F133JS datasheet(48/63 Pages) FUJITSU

48 / 63 page

MB95130M Series

Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2

(ESCR register : SCES bit

= 0, ECCR register : SCDE bit = 1)

(VCC

= 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCK

Internal clock

operation output pin :

= 80 pF + 1 TTL.

5 tMCLK*3

⎯

SCK

↑→ SOT delay time

tSHOVI

SCK, SOT

− 95

+95

Valid SIN

→ SCK↓

tIVSLI

SCK, SIN

tMCLK*3

+ 190

⎯

SCK

↓→ valid SIN hold time

tSLIXI

SCK, SIN

⎯

SOT

→ SCK ↓ delay time

tSOVLI

SCK, SOT

⎯

4 tMCLK*3

SCK

SOT

SIN

2.4 V

0.8 V

tSHOVI

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

2.4 V

0.8 V

tSCYC

tSOVLI

tIVSLI

tSLIXI

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