Philips Semiconductors

Product specification

SA5753

Audio processor – filter and control section

1997 Nov 07

6

e. A4 compensates for transmit gain variations due to manufacturing

(Pin 20). After A2a has been adjusted to set dynamic range then

that a nominal 10kHz/V VCO produces a peak deviation of 12kHz

to meet AMPS specifications.

g. A7 compensates for manufacturing tolerances in the SA5753 and

preceeding demodulator. For AMPS requirements, a 1kHz tone

with 2.9kHz deviation should produce an output signal at

of the expandor.

NAMPS and VCO Offsets

For NAMPS applications, a ‘1’ programmed into R5B3 (register 5, bit

3) will offset the transmit gain for NAMPS applications. It is

recommended that A2a and A4 be programmed after the NAMPS

option is set to compensate for manufacturing tolerances in the

NAMPS offset, itself.

When the VCO bit of R5B2 is a ‘1’, an extra gain of 6dB is provided

The SA5753 includes on-chip gain blocks and options which can be

the DFT pin (Pin 13) must be pulled LOW. In this mode, all signal

level adjustments can be made through software with no external

potentiometers required.

With DFT pulled LOW, the HPDN pin (Pin 6) is an OUTPUT having

the same value as the program bit in register 5 bit 1 (R5B1) of the

outputs can be used to control the state of the SA5752 companion

device.

Power On Reset and Power Down Modes

In order to avoid undefined states of the SA5753 when power is

initially applied, a power-on-reset circuit is incorporated which

defaults RxP and TxP such that the receive and transmit paths are

muted if a ‘high’ voltage is applied to RX MUTE and TX MUTE (Pins

12 and 18). RX MUTE and TX MUTE include on-chip pull up

resistors so, during power up, the user may apply a logic ‘1’ to these

pins or leave them floating. After power up, the registers can be

programmed and the mutes removed by a quick access write to R0.

Three software controlled low power modes are provided on the

SA5753. These are POWER DOWN (PWDN), IDLE and DENA and

can be selected by programming a ‘1’ into R6B2, R6B1 or R6B0 as

follows. In PWDN mode (R6B2=1) both the voice and data

channels are powered down with the respective I/O pins at a high

impedance. In DENA mode (R6B1=1) the voice channels are

fully active. In IDLE mode (R6B1=1, R6B0=1) both voice and data

channels are powered down. (See Table on page 8.)

The difference between selecting IDLE and PWDN is that the former

maintains the normal operational bias voltages at all voice and data

I/O pins and provides a glitch-free transfer from power down to a

fully active mode and vice-versa.

Although the POWER DOWN mode exhibits lower power

consumption, glitches may occur when transferring to an active

mode because of the previous high impedance of the I/O pins.

value as R8B7 and R5B1 in all low power modes.

bypassed. To use this mode, the DFT pin (Pin 13) is pulled HIGH,

(S13), R0B0 (S10) and R0B1 (S9), which are set to ‘1’ to enable the

receiver output. R6B2 (PWDN), which is controlled by the state of

the HPDN pin (Pin 6), which is an input in DEFAULT mode.

When HPDN is pulled HIGH, the R6B2 bit is set to ‘0’ and the

SA5753 is placed in it’s normal operating mode with all Gain Control

Blocks set to 0dB except A3, which is set to –2dB.

When HPDN is pulled LOW, the R6B2 bit is set to ‘1’ and the

SA5753 enters POWER DOWN.

There is no on-chip pull-up or pull-down structure on the HPDN pin

and so it must not be allowed to float in DEFAULT mode since the

operating mode of the SA5753 will then be undetermined.

The Tx MUTE and Rx MUTE pins must be pulled LOW to enable the

transmit and receive paths, respectively.

The VOXCTL pin (Pin 5) will follow the value of the control bit stored

in R8B7 prior to pulling DFT HIGH.

The DTMF is disabled in the DEFAULT mode.

In the default mode, with DFT (Pin 13) and HPDN (Pin 6) pulled

HIGH, the registers in the control register bit map are chained

together so that bit 0 of a register is connected to bit 7 of the

preceeding register with R0B6, R0B7, R1B6 and R1B7 bypassed,

i.e., R0B5 is connected to R1B0, R1B5 is connected to R2B0, R2B7

is connected to R3B0, etc. Bits can then be loaded as a serial

loaded at SDA it will load first into R0B0 and then will be shifted to

R8B7 after 68 clock edges.

A total of 68 clock pulses (applied at SCL) are therefore required to

completely load the registers.

In this mode of operation the contents of the register map are also

R8B7. After power up there is no reset within the registers so the

value.

Summary: To use this capability, the DFT pin and the HPDN pin

must be pulled HIGH, the serial bit stream loaded through SCL

synchronous with the negative clock edge applied at SCL for 68

clock pulses, and then the DFT pin pulled LOW.

NOTE: Default Mode is not tested in production.