SP7680EB datasheet(5/16 Pages) SIPEX

5 / 16 page

June 21-07 revH

SP7680: Complete Backlight Solution



2007 Sipex Corporation

Page 5

TIMING CHARACTERISTICS

(Typical Operating Circuit, VIN =2.7V to 5.5 V, Tj =-40°C to 125°C, unless otherwise noted. Typical

Values are at VIN=3.3V, TA=+25 °C)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Serial Clock Frequency

fSCL

400

kHz

Bus Free Time Between a

STOP and a START

tBUF

1.3

µs

Hold Time, Repeated

START Condition

t HD_STA

0.6

µs

Repeated START Condition

Setup Time

TSU,STA

0.6

µs

STOP Condition Setup Time

tSU,STO

0.6

µs

Data Hold Time

tHD,DAT(OUT)

225

900

Input Data Hold Time

tHD,DAT(IN)

900

Data Setup Time

tSU,DAT

100

SCL Clock Low Period

tLOW

1.3

µs

SCL Clock High Period

tHIGH

0.6

µs

Rise Time of Both SDA and

SCL Signals, receiving

(Notes2, 3)

20+

0.1Cb

300

Fall Time of Both SDA and

SCL Signals, Receiving

(Note2, 3)

20+

0.1Cb

300

Fall Time of SDA

Transmitting

tF.TX

(Note2, 3, 4)

20+

0.1Cb

250

Pulse Width of Spike

Suppressed

tSP

(Note5)

Capacitive Load for Each

Bus Line

(Note 2)

400

I²C startup time after UVLO

clears

Tsrt

(Note 2)

µs

Note 1: All parameters tested at TA=25 °C. Specifications over temperature are guaranteed by design.

Note 2: Guaranteed by design.

Note 3: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x

VDD.

Note 4: ISINK ≤6mA. Cb =total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD

and 0.7 VDD.

Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

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