 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
SN74LVC166A 데이터시트(PDF) 6 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
SN74LVC166A 데이터시트(HTML) 6 Page - Texas Instruments |
|
|
6 / 23 page  5.6 Timing Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT MIN MAX tW Pulse duration CLK 1.2 V ± 0.1 V 7 ns tSU Setup time SH/LD high before CLK↑ 1.2 V ± 0.1 V 16.5 ns tSU Setup time SER before CLK↑ 1.2 V ± 0.1 V 10.1 ns tSU Setup time CLK INH before CLK↑ 1.2 V ± 0.1 V 1 ns tSU Setup time Data before CLK↑ 1.2 V ± 0.1 V 10 ns tSU Setup time CLR inactive before CLK↑ 1.2 V ± 0.1 V 10.1 ns tH Hold time SER data after CLK↑ 1.2 V ± 0.1 V 0.4 ns tH Hold time Parallel data after SH/LD↓ 1.2 V ± 0.1 V 1.8 ns tH Hold time SH/LD high after CLK↑ 1.2 V ± 0.1 V 0 ns tH Hold time CLK INH high after CLK↑ 1.2 V ± 0.1 V 0.4 ns tH Hold time Data after CLK↑ 1.2 V ± 0.1 V 1 ns tW Pulse duration CLR low 1.5 V ± 0.15 V 6.9 ns tW Pulse duration SH/LD low 1.5 V ± 0.15 V 6.9 ns tW Pulse duration CLK 1.5 V ± 0.15 V 7 ns tSU Setup time SH/LD high before CLK↑ 1.5 V ± 0.15 V 10 ns tSU Setup time SER before CLK↑ 1.5 V ± 0.15 V 10.1 ns tSU Setup time CLK INH before CLK↑ 1.5 V ± 0.15 V 1 ns tSU Setup time Data before CLK↑ 1.5 V ± 0.15 V 10 ns tSU Setup time CLR inactive before CLK↑ 1.5 V ± 0.15 V 10.1 ns tH Hold time SER data after CLK↑ 1.5 V ± 0.15 V 1.2 ns tH Hold time Parallel data after SH/LD↓ 1.5 V ± 0.15 V 1.9 ns tH Hold time SH/LD high after CLK↑ 1.5 V ± 0.15 V 1 ns tH Hold time CLK INH high after CLK↑ 1.5 V ± 0.15 V 0.6 ns tH Hold time Data after CLK↑ 1.5 V ± 0.15 V 1.8 ns tW Pulse duration CLR low 1.8 V ± 0.15 V 6.9 ns tW Pulse duration SH/LD low 1.8 V ± 0.15 V 6.9 ns tW Pulse duration CLK 1.8 V ± 0.15 V 7 ns tSU Setup time SH/LD high before CLK↑ 1.8 V ± 0.15 V 8 ns tSU Setup time SER before CLK↑ 1.8 V ± 0.15 V 10.1 ns tSU Setup time CLK INH before CLK↑ 1.8 V ± 0.15 V 1 ns tSU Setup time Data before CLK↑ 1.8 V ± 0.15 V 8 ns tSU Setup time CLR inactive before CLK↑ 1.8 V ± 0.15 V 10.1 ns tH Hold time SER data after CLK↑ 1.8 V ± 0.15 V 0.2 ns tH Hold time Parallel data after SH/LD↓ 1.8 V ± 0.15 V 0.8 ns tH Hold time SH/LD high after CLK↑ 1.8 V ± 0.15 V 0 ns tH Hold time CLK INH high after CLK↑ 1.8 V ± 0.15 V 0.3 ns tH Hold time Data after CLK↑ 1.8 V ± 0.15 V 1 ns tW Pulse duration CLR low 2.5 V ± 0.2 V 5.4 ns tW Pulse duration SH/LD low 2.5 V ± 0.2 V 5.4 ns tW Pulse duration CLK 2.5 V ± 0.2 V 4.5 ns tSU Setup time SH/LD high before CLK↑ 2.5 V ± 0.2 V 4.5 ns tSU Setup time SER before CLK↑ 2.5 V ± 0.2 V 5.9 ns tSU Setup time CLK INH before CLK↑ 2.5 V ± 0.2 V 1 ns SN74LVC166A SCLSA15 – MAY 2024 www.ti.com 6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: SN74LVC166A |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
