6 Detailed Description

6.1 Overview

When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and

the enable time of the memory usually are less than the typical access time of the memory. This means that the

effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two

active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A

24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter.

An enable input can be used as a data input for demultiplexing applications (see Application Information).

6.2 Functional Block Diagram

Figure 6-1. Logic Diagram (Positive Logic)

6.3 Device Functional Modes

Table 6-1. Function Table

ENABLE INPUTS

SELECT INPUTS

OUTPUTS

G1

G2A

G2B

C

B

A

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

X

H

X

X

X

X

H

H

H

H

H

H

H

H

X

X

H

X

X

X

H

H

H

H

H

H

H

H

L

X

X

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

L

L

L

H

H

H

H

H

H

H

H

L

L

L

L

H

H

L

H

H

H

H

H

H

H

L

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

L

H

H

H

H

H

L

H

H

H

H

H

L

L

H

L

L

H

H

H

H

L

H

H

H

H

L

L

H

L

H

H

H

H

H

H

L

H

H

CD54ACT138, CD74ACT138

SCHS329C – JANUARY 2003 – REVISED JULY 2024

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