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SC28L92 데이터시트(PDF) 38 Page - NXP Semiconductors

부품명 SC28L92
상세설명  3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART
PDF  44 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC28L92 데이터시트(HTML) 38 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
38
NOTES:
1.
INTRN or OP3-OP7 when used as interrupt outputs.
2.
The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
VM
VOL +0.5V
VOL
WRN
INTERRUPT1
OUTPUT
tIR
VM
VOL +0.5V
VOL
RDN
INTERRUPT1
OUTPUT
tIR
SD00136
Figure 10. Interrupt Timing (80xxx mode)
C1 = C2
∼ 24pF FOR CL = 20pF
tCLK
tCTC
tRx
tTx
X1/CLK
CTCLK
RxC
TxC
tCLK
tCTC
tRx
tTx
VCC
470
Ω
X1
X2*
CLK
*NOTE: X2 MUST BE LEFT OPEN.
X2
3.6864MHz
X1
C1
C2
SC28L92
NOTE:
RESISTOR REQUIRED
FOR TTL INPUT.
TO UART
CIRCUIT
50k
Ω
to
100k
Ω
3pF
3pF
C1 and C2 should be chosen according to the crystal manufacturer’s specification.
C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins.
Gain at 3.6864MHz: 9 to 13 dB
2pF
4pF
Package capacitance approximately 4pF.
SD00695
PARASITIC CAPACITANCE
PARASITIC CAPACITANCE
Figure 11. Clock Timing



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