ASAHI KASEI

[AK6514C]

DAP04E-00

2005/03

- 5 -

Pin Description

When CS changes high level to low level, the AK6514C can receive the instructions.

CS should be kept low level while receiving op-code, address and data, and while outputting

data.

When CS is high level, SO indicate Hi-Z.

The SCK clock pin is the synchronous clock input for input/output data.

The op-code, address, and data are written to the SI pin.

The SO pin outputs the data from memory array and status register.

The WP pin controls the write function to the status register.

When the WPEN bit in the status register is "0", the function of WP pin becomes disable.

Then the status register can be programmable when the WEN bit in the status register is "1".

And it does not depend on the status of WP pin.

When the WPEN bit is "1", the function of WP is enabled.

Then the status register can not

be programmable when the WEN bit is "1" and the status of WP pin is low.

When the WPEN bit is "1", WP pin is high and WEN bit is "1", AK6514C can accept the

WRITE instruction to the status registers.

During the instruction input, WP pin should keep high or low level.

The HOLD pin can hold the data transfer.

When the HOLD pin changes hi to low while the

SCK is low, the data transfer is held.

And the transfer starts when the HOLD pin changes

low to high while the SCK is low.

While the holding the data transfer, AK6514C ignores the

clock signal on SCK pin.