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PL611S-19-XXXTC-R 데이터시트(PDF) 1 Page - PhaseLink Corporation |
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PL611S-19-XXXTC-R 데이터시트(HTML) 1 Page - PhaseLink Corporation |
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1 / 8 page ![]() (Preliminary)PL611s-19 0.5kHz-55MHz MHz to KHz Programmable Clock TM 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1 FEATURES • Designed for Very Low-Power applications • Offered in Tiny GREEN/RoHS compliant packages o 6-pin DFN (2.0mmx1.3mmx0.6mm) o 6-pin SC70 (2.3mmx2.25mmx1.0mm) o 6-pin SOT23 (3.0mmx3.0mmx1.35mm) • Input Frequency: o Reference Input: 1MHz to 200MHz o Non PLL mode, Ref input down to 10kHz • Accepts >0.1V reference signal input voltage • Output frequency up to 55MHz CMOS. o <65MHz @ 1.8V operation o <90MHz @ 2.5V operation o <125MHz @ 3.3V operation • One programmable I/O pin can be configured as Power Down (PDB) input, output Enable (OE), or Frequency Selection Switching input. • Disabled outputs programmable as HiZ or Active Low. • Low current consumption: o <1.0mA with 27MHz & 32kHz outputs o < 5 A when PDB is activated • Single 1.8V, 2.5V, or 3.3V ± 10% power supply • Operating temperature range from -40°C to 85°C DESCRIPTION The PL611s-19 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611s-19 offers the versatility of using a single Reference Clock input and producing up to two (kHz or MHz) system clock outputs. Designed for low-power applications with very stringent space requirement, PL611s-19 consumes <1.0mA, while producing 2 distinct outputs of 27MHz and 32kHz. The power down feature of PL611s-19, when activated, allows the IC to consume less than 5 A of power. PL611s-19 fits in a small DFN, SC70, or SOT23 package. Cascading of the PL611s-19 with other PhaseLink programmable clocks allow generating system level clocking requirements, thereby reducing the overall system implementation cost. In addition, one programmable I/O pin can be configured as Power Down (PDB) input, Output Enable (OE), or Frequency switching (FSEL). CLK1 can be programmed as (CLK0, FREF, FREF /2) output. BLOCK DIAGRAM Phase Detector Charge Pump Loop Filter VCO FIN R-Counter (5-bit) FVCO = FREF * (2 * M/R) FOUT = FVCO / (2 * P) CLK [0:1] FREF Programming Logic OE, PDB, FSEL M-Counter (8-bit) P-Counter (14-bit) Programmable Function |
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