STPMIC25BPQR datasheet(52/145 Pages) STMICROELECTRONICS

52 / 145 page

5.4.6.2

Regulator independent reset detailed behaviors (PWRCTRL_RST)

The independent reset feature is controlled from a PWRCTRLx input pin (PWRCTRL_SRC[1:0]) and it is enabled

by setting the PWRCTRL_RST bit. This feature allows a regulator to reset to its default NVM value from an AP

hardware signal “on the fly” (which cannot be done by I2C access).

When the PWRCTRLx input pin is active, regulator xxx is forced into OFF mode. xxx_MAIN_CR and xxx_ALT_CR

registers are both reset to default value (NVM default value is reloaded in both registers from the related NVM

shadow register).

When the PWRCTRLx input pin is inactive, regulator xxx is controlled from xxx_MAIN_CR register content.

Figure 16 provides an example to illustrate Section 5.4.6.2 using the PWRCTRL3 to control the LDO2

independent reset.

Assumptions and settings for the Figure 17 example:

LDO2 reset value (from the NVM):

•

LDO2_MAIN_CR[VOUT] = 2.9 V

•

LDO2_MAIN_CR[EN] = 1

Software settings:

PWRCTRL3_POL = 0; // PWRCTRL3 active low = bypass

// LDO2 settings

LDO2_PWRCTRL_CR[PWRCTRL_SEL[1:0]] = 3; // PWRCTRL3 as LDO2 control source

LDO2_PWRCTRL_CR[PWRCTRL_DLY_H[1:0]] = 0; // no delay on PWRCTRL3 going high for LDO2

LDO2_PWRCTRL_CR[PWRCTRL_DLY_L[1:0]] = 0; // no delay on PWRCTRL3 going low for LDO2

LDO2_PWRCTRL_CR[PWRCTRL_RST] = 1; // enable the PWRCTRL3 input to control LDO2 independent reset

Figure 17. Regulator independent reset behaviors example

PWRCTRL3

LDO2

LDO2OUT

software disable

LDO2 and set vout

to 1.8 V

2.9 V

0 V

LDO2_MAIN_CR:

Vout = 1.8V

EN = 0

LDO2_MAIN_CR:

Vout = 2.9V

EN = 1

Crash:

the AP asserts

PWRCTRL3 for 3 ms

>3 ms

software set vout

to 3.3 V

LDO2_MAIN_CR:

Vout = 3.3V

EN = 1

2.9 V

3.3 V

Crash:

the AP asserts

PWRCTRL3 for 3 ms

>3 ms

LDO2_MAIN_CR:

Vout = 2.9V

EN = 1

2.9 V

christophe belet

ST Microelectronics

LDO2_MAIN_CR:

Vout = 2.9V

EN = 1

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 52/145

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