Data Sheet

ADN2913

Rev. B | Page 17 of 35

Table 13. D/PLL Control Register, DPLLA (Address 0x10)

Bits

Bit Name

Bit Description

D7:D5

Reserved to 0.

D4:D3

EDGE_SEL[1:0]

Edge for phase detection. See the Edge Select section for more information.

00 = rising and falling edge data.

01 = rising edge data.

10 = falling edge data.

11 = rising and falling edge data.

D2:D0

TRANBW[2:0]

Transfer bandwidth. Scales the transfer bandwidth. Default value is 4, resulting in the 8GFC

default BW shown in Table 2. See the Transfer Bandwidth section for more information.

Transfer BW = Default BW × (TRANBW[2:0]/4)

Table 14. D/PLL Control Register, DPLLD (Address 0x13)

Bits

Bit Name

Bit Description

D7:D3

Reserved to 0.

D2

ADAPTIVE_SLICE_EN

Adaptive slice enable. 1 = enables automatic slice adjust.

D1:D0

DLL_SLEW[1:0]

DLL slew. Sets the BW of the DLL. See the DLL Slew section for more information.

Table 15. Phase Control Register, Phase (Address 0x14)

Bits

Bit Name

Bit Description

D7:D4

Reserved to 0.

D3:D0

SAMPLE_PHASE[3:0]

Adjust the phase of the sampling instant for data rates above 5.65 Gbps in steps of 1/32 UI. This

register is in twos complement format. See the Sample Phase Adjust section for more

information.

Table 16. Slice Level Control Register, Slice (Address 0x15)

Bits

Bit Name

Bit Description

D7

Extended slice

Extended slice enable.

0 = normal slice mode.

1 = extended slice mode.

D6:D0

Slice[6:0]

Slice is a digital word that sets the input threshold. See the Slice Adjust section for more information.

When slice[6:0] = 0000000, the slice function is disabled.

Table 17. Input Stage Programming Register, LA_EQ (Address 0x16)

Bits

Bit Name

Bit Description

D7

RX_TERM_FLOAT

Rx termination float.

0 = termination common-mode driven.

1 = termination common-mode floated (VCC = 1.2 V).

D6:D5

INPUT_SEL[1:0]

Input stage select.

00: limiting amplifier.

01: equalizer.

10: 0 dB EQ.

11: undefined.

D4

ADAPTIVE_EQ_EN

Enable adaptive EQ.

0 = manual EQ control.

1 = adaptive EQ enabled.

D3:D0

EQ_BOOST[3:0]

Equalizer gain. These bits set the EQ gain. See the Passive Equalizer section for more information.