| 전자부품 데이터시트 검색엔진 |
|
TDA5345HT 데이터시트(PDF) 14 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
TDA5345HT 데이터시트(HTML) 14 Page - NXP Semiconductors |
|
14 / 44 page ![]() 1999 June 10 14 Philips Semiconductors Preliminary specification 5 V spindle & VCM driver combo TDA5345HT Commutation control DELAYS The spindle block contains both the low-side and high-side drivers configured as a H bridge for a three phase DC brushless, sensorless motor. In each of the six possible states, two outputs are active, one sourcing current and one sinking current. The third output presents a high impedance to the motor which enables measurement of the BEMF in the corresponding motor coil. The back-EMF comparator output (available on pin SpinDigOut) is processed by the commutation logic circuit to calculate the correct time for the next commutation, which will change the output state. The commutation block measures then the time between 2 consecutive zero-crossings and determines the actual commutation time and the next motor coils state. All the following situations must be taken into account: => Start up, No start, Backwards spin, Run and Manual commutation. The commutation logic keeps the motor spinning by commutating the motor each time a zero-crossing is detected. The delay between the zero-crossing and the actual output driver change is either internally calculated or programmable via the serial port (useful at start-up: no delay has been measured!). The internal commutation clock can be monitored on pin SpinDigOut (44). The falling edges are the relevant informations: they are caused by the zero-crossings. If preferred, SpinDigOut can be set to become the back-EMF comparator output, to check if the spindle is already spinning at power up for instance. If the spindle outputs are floating, don’t forget to bias them, using the “BiasCT” bit, before considering the BemfCompOut value. Fig.6 and Fig.7 show typical motor commutation timing diagrams. SpinMotA SpinMotB SpinMotC Commutation BemfCompOut L L F HH F H F LL F H F HH F L L Fig.7 Input commutations to output drivers Clock Zero-crossing State Code 0 1 2 3 4 5 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |