24LCS21-SLASHP datasheet(8/24 Pages) MICROCHIP

8 / 24 page

24LCS21

DS21127F-page 8

4.0

WRITE OPERATION

4.1

Byte Write

Following the Start signal from the master, the slave

address (4 bits), three zero bits (000) and the R/W bit,

which is a logic low, are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow after it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte

transmitted by the master is the word address and will

be written into the Address Pointer of the 24LCS21.

After receiving another Acknowledge signal from the

24LCS21, the master device will transmit the data word

to be written into the addressed memory location. The

24LCS21

acknowledges

again

and

the

master

generates a Stop condition. This initiates the internal

write cycle, and during this time the 24LCS21 will not

generate Acknowledge signals (Figure 4-1).

It is required that VCLK be held at a logic high level

during command and data transfer in order to program

the device. This applies to both byte write and page

write operation. Note, however, that the VCLK is ignored

during the self-timed program operation. Changing

VCLK from high-to-low during the self-timed program

operation will not halt programming of the device.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

VCLK WRITE ENABLE TIMING

Bus Activity

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

VCLK

Activity

TSPVL

TSU:STO

THD:STA

TVHST

VCLK

SDA

SCL

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