24C32A

DS21163E-page 8

 2004 Microchip Technology Inc.

6.3

Contiguous Addressing Across

Multiple Devices

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to 256K

bits by adding up to eight 24C32A's on the same bus.

In this case, software can use A0 of the control byte as

address bit A12, A1 as address bit A13, and A2 as

address bit A14.

6.4

Sequential Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24C32A transmits the

first data byte, the master issues an acknowledge as

opposed to the stop condition used in a random read.

This acknowledge directs the 24C32A to transmit the

next sequentially addressed 8-bit word (Figure 6-3).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge but will gen-

erate a stop condition.

To provide sequential reads the 24C32A contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation. The internal address pointer will

automatically roll over from address 0FFF to address

000 if the master acknowledges the byte received from

the array address 0FFF.

FIGURE 6-2:

RANDOM READ

FIGURE 6-3:

SEQUENTIAL READ

0000

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

CONTROL

S

T

O

P

A

C

K

N

O

A

C

K

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

A

C

K

A

C

K

A

C

K

S

T

A

R

T

S

SP

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A

C

K

N

O

A

C

K

A

C

K

A

C

K

A

C

K

DATA n

DATA n + 1

DATA n + 2

DATA n + x

S

T

O

P

P